Generally speaking, a memory controller accesses a memory module, e.g., a dynamic random access memory (DRAM) module. When the memory controller issues a write command, data is transmitted from the memory controller to a DRAM chip of the memory module and stored therein. When the memory controller issues a read command, data is transmitted from the DRAM chip of the memory module to the memory controller.
Taking a double data rate (DDR) memory module or a DDR dual in-line memory module (DDR DIMM) for example, a DDR transaction comprises steps below.
According to a command clock, the memory controller issues a command via command lines and address lines. In a next command clock, each of DDR memory modules accesses the command via the command lines and the address lines, and determines a DDR memory module associated with the command. After that, each of DRAM chips in the associated DDR memory module prepares to access data according to the command.
When the command is a read command, each of the DRAM chips begins to drive a data serial (DQ) signal and a data strobe (DQS) signal. When the command is a write command, the DQ signal and the DQS signal are driven by the memory controller. After that, the DQ signal and the DQS signal begin toggling. For example, when a memory module has eight DRAM chips, there are 64 DQ signals for transmitting data and 8 DQS signals for transmitting data clocks.
Refer to FIG. 1A and FIG. 1B showing signals of a DDR memory module. A memory controller 230 controls four DDR memory modules. For brevity, only two DDR memory modules 100 and 200 are illustrated in FIG. 1A and FIG. 1B. FIG. 1A shows signals outputted by the memory controller 230, including four command clock signals CMDCLK0 to CMDCLK3, four chip select signals CS0 to CS3, command signals, and address signals. The first DDR memory module 100 comprises eight DRAM chips 101 to 108, and a register 120. The second DDR memory module 200 comprises eight DRAM chips 201 to 208, and a register 220. The command signals and the address signals generated by the memory controller 230, e.g., address signals A0 to A13, a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable (WE) signal, are transmitted to both the registers 120 and 220 of the DDR memory modules 100 and 200.
The memory controller 230 outputs four command clock signals CMDCLK0 to CMDCLK3 and four chip select signals CS0 to CS3 to either the register 120 of the DDR memory module 100 or the register 220 of the DDR memory module 200. According to the signals in FIG. 1A, addresses for reading data from or writing data to the DRAM chips 101 to 108 of the first DDR memory module 100 or the DRAM chips 201 to 208 of the second DDR memory module 200 are determined.
Refer to FIG. 1B showing DQ signals and DQS signals of DDR memory modules. The first DDR memory module 100 comprises eight DRAM chips 101 to 108, and the second DDR memory module 200 comprises eight DRAM chips 201 to 208. Each of the chips needs eight DQ signals in conjunction with one DQS signal, to provide eight byte lanes. Data transfer rate of each byte lane is controlled by one corresponding DQS signal.
Referring to FIG. 1B, the first DRAM chips 101 and 201 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ0 to DQ7 and a DQS signal DQS0. The second DRAM chips 102 and 202 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ8 to DQ15 and a DQS signal DQS1. The third DRAM chips 103 and 203 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ16 to DQ23 and a DQS signal DQS2. The fourth DRAM chips 104 and 204 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ24 to DQ31 and a DQS signal DQS3. The fifth DRAM chips 105 and 205 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ32 to DQ39 and a DQS signal DQS4. The sixth DRAM chips 106 and 206 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ40 to DQ47 and a DQS signal DQS5. The seventh DRAM chips 107 and 207 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ48 to DQ55 and a DQS signal DQS6. The eighth DRAM chips 108 and 208 of the first memory module 100 and the second memory module 200 are coupled to the memory controller 300 through DQ signals DQ56 to DQ63 and a DQS signal DQS7.
Accordingly, when the command is reading the first DDR memory module 100, eight DRAM chips 101 to 108 of the first DDR memory module 100 begin to drive the DQ signals DQ0 to DQ63 and the DQS signals DQS0 to DQS7. When the command is writing into the first DDR memory module 100, the DQ signals DQ0 to DQ63 and the DQS signals DQS0 to DQS7 are driven by the memory controller 230. After that, the DQ signals DQ0 to DQ63 and the DQS signals DQS0 to DQS7 begin toggling.
Refer to FIG. 2A showing a diagram of DQ signals and DQS signals when the command is a read command. According to the DDR specification, when a DDR module transmits data, the DQ signals and the DQS signals are aligned with each other. Taking the DQ signals DQ0 to DQ7 and the DQS signal DQS0 for example, data of the DQ signals DQ0 to DQ7 needs to be aligned with rising edges and falling edges of the DQS signal DQS0. That is, when the command is a read command, DDR chips output DQ signals and DQS signals, which are received by the memory controller 230. Generally, DDR chips generate DQS signals with reference to positive-phase and negative-phase clock signals (CLK and CLK, not shown) provided by the memory controller 230.
Refer to FIG. 2B showing a diagram of the DQS signal DQS0, adjusted by the memory controller, and the DQ signals DQ0 to DQ7. Upon receiving the aligned DQS signal DQS0 and the DQ signals DQ0 to DQ7, the memory controller 230 delays a phase of the DQS signal DQS0 by 90 degrees, and latches data on the byte lanes (i.e., DQ0 to DQ7) via the DQS signal DQS0 delayed by 90 degrees (i.e., DQS0_90).
FIG. 3 shows a DQS signal calibrating circuit inside a memory controller according to the prior art. The DQS signal calibrating circuit is a master-slave delay locked loop (DLL) for delaying a DQS signal. The master-slave DLL comprises a master delay chain 300, a slave delay chain 320, and a phase detector 330. The slave delay chain 320 is a replica of the master delay chain 300, i.e., the slave delay 320 has same fabrication conditions as the master delay chain 300, and is arranged adjacently to the master delay chain 300 to match with each other. The master delay chain 300 comprises eight buffers 301 to 308 connected in series, and each of the buffers 301 to 308 is capable of generating an output signal. A positive-phase clock signal CLK generated by a memory controller enters the first buffer 301 of the master delay chain 300 and the phase detector 330, and an output signal of the eighth buffer 308 of the master delay chain 300 enters the phase detector 330. Therefore, the phase detector 330 compares the positive-phase clock signal CLK and the output signal of the eighth buffer 308 to generate a control voltage Vctl to control propagation delay of the buffers 301 to 308 of the master delay chain 300, such that a fixed phase difference exists among the eight output signals. Referring to FIG. 2B, the phase difference is 45 degrees. The output signal of the first buffer 301 is the positive-phase clock signal CLK delayed by 45 degrees. The output signal of the second buffer 302 is the positive-phase clock signal CLK delayed by 90 degrees. The output signal of the third buffer 303 is the positive-phase clock signal CLK delayed by 135 degrees. The output signal of the fourth buffer 304 is the positive-phase clock signal CLK delayed by 180 degrees. The output signal of the fifth buffer 305 is the positive-phase clock signal CLK delayed by 225 degrees. The output signal of the sixth buffer 306 is the positive-phase clock signal CLK delayed by 270 degrees. The output signal of the seventh buffer 307 is the positive-phase clock signal CLK delayed by 315 degrees. The output signal of the eighth buffer 308 is the positive-phase clock signal CLK delayed by 360 degrees, which is the same as the phase of the positive-phase clock signal CLK.
The slave delay chain 320 comprises eight buffers 321 to 328 connected in series. The controls ends of the buffers 321 to 328 receive the control voltage Vw, and each of the buffers 321 to 328 is capable of delaying a fixed phase difference. The first buffer 321 of the slave delay chain 320 receives DQS signal.
Therefore, the control voltage Vctl simultaneously controls the buffers 301 to 308 of the master delay chain 300 and the buffers 321 to 328 of the slave delay chain 320, such that propagation delay of the buffers 301 to 308 and 321 to 328 is the same. Accordingly, the output signal of the second buffer 322 of the slave delay chain 320 is the DQS signal delayed by 90 degrees (referred to as DQS_90).
A matching degree between the master delay chain 300 and its replica, i.e., the slave delay chain 320, is proportional to 1/√{square root over (W·L)}, where W and L represent a channel width and a channel length of a transistor, respectively. As the fabrication technology develops, the channel width and channel length of the transistor may become smaller and smaller. Therefore, the matching degree between the master delay chain 300 and the slave delay chain 320 becomes worse as the fabrication technology develops, such that a phase difference between the output signal of the second buffer 322 of the slave delay chain 320 and the DQS signal cannot be exactly 90 degrees.